A PLL is an electronic circuit that controls an oscillator so that the oscillator maintains a constant phase angle relative to a reference signal. Clock recovery circuits typically use a phase-locked loop circuit to track and reduce the phase offset between clock and data signals. The basic architecture of a simple PLL circuit is illustrated in FIG. 1. PLL circuits are used in applications such as generating a clean periodic signal from a noisy signal, frequency multiplication, and clock and data recovery.
A typical voltage-controlled oscillator or (“VCO”) 100 may be used to generate an output 102 which is a periodic signal at a desired frequency. The phase locked loop is designed to allow the VCO output 102 to be phase locked to an external reference signal 104. The external reference signal 104 may, for example, be a periodic signal such as a sinusoidal or square wave at a fixed frequency (e.g., for frequency synthesizers and multipliers applications), a modulated waveform (e.g., for a demodulator application), or a non-periodic waveform with timing information such as a data waveform (e.g., for clock and data recovery applications). The phase of the VCO output 102 and the reference signal are compared by phase detector 106, which generates an output signal 108 which indicates whether VCO output signal 102 is earlier or later than the reference signal. Phase detector output 108 is filtered by a loop filter, typically an integrator 110, which generates a control voltage 112 that adjusts the VCO output and aligns the VCO output to the reference frequency and phase.
The implementation of integrator 110 may use a low-pass filter or may, in the alternative, use digital methods to integrate the output of phase detector 106. Digital integrators are often desirable because such integrators offer design flexibility compared to analog integrators. However, such digital integrators are often more complex than analog integrators and, at relatively high frequencies, the digital integrators consume more power than analog integrators.
The basic architecture of a delay locked loop is illustrated in FIG. 2. A DLL is typically a digital device similar to a PLL, however, a DLL uses a variable delay or phase shifter element instead of a voltage controlled oscillator. A periodic input signal 200 is provided to the delay locked loop. The signal is delayed by a variable delay or phase shifter 202, generating an output signal 204 which is a delayed version of the input signal. The DLL output signal 204 can be delay locked to the reference input 206 if the periodic input 200 is relatively close in frequency to the reference input 206 and if the variable delay 202 can be varied in such a way as to ensure that the phase of the output 204 tracks the phase of the reference input 206.
The delay locked loop circuit provides the phase tracking mechanism by using a phase detector 208 that compares the relative phase of the output 204 and the reference 206, and by generating an output 210 that is proportional to the difference in phase. The phase difference is integrated by an integrator 212, generating a control voltage 214 to adjust the delay in variable delay device 202, essentially trying to zero out the difference in phase between output 204 and reference 206. The external reference signal 206 may be a periodic signal such as a sinusoidal or square wave at a fixed frequency (e.g., for clock synthesizers and multipliers applications), or a non-periodic waveform with timing information such as a data waveform (e.g., for clock and data recovery applications).
FIG. 3 illustrates, schematically, a prior art early/late transition based phase detector 300 used in PLL or DLL based clock and data recovery. Phase detector 300 may be substituted for phase detector 208 of FIG. 2 to form a delay locked loop circuit suitable for reducing phase offset between clock and data signals. Phase detector 300 contains a first flip-flop 311, second flip-flop 312, third flip-flop 313, and fourth flip-flop 314. Phase detector 300 receives a data wave form at input 301, and a clock input 320 from the VCO 100 or variable delay 202. The outputs of phase detector 300 are late output 303, early output 305, and data output 302. The flip-flops of device 300 are illustrated as being D flip-flops, with flip-flop 312, 313, and 314 being positive edge-triggered and flip-flop 311 being negative edge-triggered. It is known in the art that the output of a D flip-flop latches the input at the time of the triggering. Phase detector 300 is configured to provide a late output signal 303 for every clock cycle in which the reference signal lags behind the data signal, and to provide an early output signal 305 for every clock cycle in which the reference signal leads the data signal.
Phase detector 300 is incorporated into a DLL loop filter such as that shown in FIG. 4. VCO 400 provides phase selector 402 with a multi-phase periodic inputs that are close to but not necessarily equal to the desired clock frequency for the clock signal 422. For example, the frequency may be obtained through either digital control of the VCO tuning voltage or by placing the VCO in a PLL with an appropriate reference input. Phase detector 401 receives an input data signal 421, and a clock signal 422 from phase selector 402. Phase detector 401 compares the clock “feedback” signal 422 and the data signal 421 and generates early signal 403 and late signal 405 which are provided to integrator 412. Integrator 412 integrates (i.e., counts) the number of early and late pulses. The average early and late information changes relatively slowly, and may be sub-sampled by sub sampler 415 at, for example, one tenth the clock rate of the integration. The output of sub sampler 415 is a digital control word which is provided to phase select device 402 for selection of a phase from VCO 400.
That being said, difficulties and drawbacks exist due to the high frequency operation of the integrator. In order to process high frequency input data, digital integrators are configured to count early and late pulses at high frequencies. High frequency integrator operation typically results in high power consumption, heat dissipation problems, and the design of complex, and accordingly expensive, integrators that are able to perform high frequency integration. Thus, due to the need for ever increasing communication bandwidth, there is a need for a more efficient method and apparatus for implementation of digital integrators for high frequency phase locked loop and delay locked loop circuits.